A K-band CMOS Differential Vackar VCO With the Gate Inductive Feedback
Nguyen, T. N.; Lee, J.-W.

This paper presents a K-band differential Vackar VCO.  You might be thinking, what is a Vackar VCO?  It is just a Colpitts oscillator with a couple of additional capacitors.  This paper adds an additional gate inductor to improve startup performance of the Vackar oscillator.  The phase noise is reported to be several dB better than an equivalent Colpitts.

Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks
Zou, Q.; Ma, K.; Yeo, K. S.; Lim, W. M.

A Ku-band VCO with dual LC tanks is presented in the paper.  A triple-coil transformer provides strong coupling between the two LC tanks.  The claim is made that this architecture provides superior results, but a comparison of other VCOs shows a cross-coupled architecture with similar results.  The phase noise of -117.4dBc/Hz @ 1MHz offset seems to be a conveniently chosen point.  The measured phase noise plot shows several dB worse noise at a frequency offset slightly lower than 1MHz.

A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique
Lee, I-T.; Lu, H.-Y.; Liu, S.-I.

A 6-GHz all-digital fractional-N PLL is presented with a FIR-embedded noise filtering technique.  The measured out-of-band phase noise is improved with the noise filtering circuit.  The benefit of this architecture is unclear, however, because it seems that similar results could be obtained by simply adjusting the PLL bandwidth.

A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers
Ucar, A.; Cetin, E.; Kale, I.

A new continuous-time delta-sigma modulator is presented that is intended for use in RF subsampling receivers. The architecture is analyzed but not realized.  Real time tuning of the loop filter is noted as an obstacle in a practical realization.

Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC
Lee, S. M.; Taleie, S. M.; Saripalli, G. R.; Seo, D.

This paper presents an analysis of DAC output noise that is caused by the phase noise of the DAC clock.  The analysis is presented in the context of phase noise induced by TX leakage, but could apply to other cases as well.

A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors
Italia, A.; Ippolito, C. M.; Palmisano, G.

This paper shows a lower power LC VCO with a wide tuning range.  The wide range is achieved by using a switched inductor.  The concept was proven on a 90nm design with a VCO range of 1.13GHz – 1.90GHz.  The results look promising, but may have limited use in higher speed situations where the VCO inductor is small.  In such cases, the switch resistance may cause too much degradation of the tank quality factor for this to be a useful technique.

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector
Tan, Y. S.; Yeo, K. S.; Boon, C. C.; Do, M. A.

This papers shows a dual-loop CDR circuit with a new linear phase detector.  An unbalanced charge pump is used to compensate for the unbalanced pulse-width of the phase detector.

Analysis and Optimization of SFDR in Differential Active-RC Filters
Meghdadi, M.; Bakhtiar, M.

This paper presents a method for optimizing active-RC filters to achieve optimal SFDR.

Design and Analysis of a Class-D Stage With Harmonic Suppression
Fritzin, J.; Svensson, C.; Alvandpour, A.

This papers presents a low-power Class-D stage with low harmonic content in the output waveform.

An Experimental Method to Extract the Phase-Sensitivity of Oscillators to Noise Perturbations
Maffezzoni, P.

This papers shows an interesting experimental technique to measure the phase-sensitivity of oscillators to noise signals.  Not sure if this solves a real problem, given the simulation tools that are available that can simulate phase noise with good accuracy.  But from a strictly academic point of view, this is an interest method to verify the fundamentals of phase noise theory that has been presented in other work.

Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems
Weddell, A. S.; Merrett, G. V.; Al-Hashimi, B. M.

The paper describes a photovoltaic (PV) energy harvesting suitable for indoor use.  A maximum power point tracking circuit (MPPT) is shown based on a sample-and-hold circuit.  The sampling frequency and bias current of the MPPT circuit is optimized to allow use in low light (indoor) environments.

A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL
Liu, D.; Basedau, P.; Helfenstein, M.; Wei, J.; Burger, T.; Chen, Y.

This papers presents a model to examine limit cycle and spurious behavior in bang-bang all-digital phase locked loops.  The model utilizes sigma delta modulator (SDM) analysis to capture the quantization effects of the DCO and the bang-bang phase detector.

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver
Chiou, H.-K.; Lin, K.-C.; Chen, W.-H.; Juang, Y.-Z.

This paper describes a biasing technique for a inverter stage that drives a double balanced mixer.  The pmos transistor is biased through a resistor to the output of the inverter.  The nmos transistor is biased separately.

Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints
Bassi, M.; Bevilacqua, A.; Gerosa, A.; Neviani, A.

Great work on a very important public health issue.  Who would have thought that one transceiver architecture would be better than another for Breast Cancer Imaging?

Quantization Error Spectra Structure of a DTC Synthesizer via the DFT Axis Scaling Property
Talwalkar, S. A.

This paper presents an analysis of phase accumulator quantization in a digital to time (DTC) direct frequency synthesizer.  Using the analysis, spur values can be predicted which closely match measured results.  The analysis can also be used for a flying adder synthesizer.

A Gated FM-UWB System With Data-Driven Front-End Power Control
Zhou, B.; Qiao, J.; He, R.; Liu, J.; Zhang, W.; Lv, H.; Rhee, W.; Li, Y.; Wang, Z.

This paper presents a frequency modulated ultra-wideband (FM-UWB) transceiver system with RF submodules gated by a data-driven control signal.  The design utilizes an 8-modulo fractional-N PLL.