# Solid State Circuits, Volume 47, Issue 6

A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver
Nakamura, T.; Masuda, T.; Washio, K.; Kondoh, H.

A 59-GHz push-push voltage-controlled oscillator (VCO) is presented.  The VCO uses a loop-ground transmission line (LG-TML), which makes it possible to output both a large signal at second harmonic frequency and an adequate signal at the fundamental frequency for driving a prescalar.  The VCO achieves high output power of +1.5 dBm, while maintaining wide tuning range of 13.9 GHz (26% of the center oscillation frequency).  A new single turn inductor geometry is also presented showing improved performance vs. an octagonal inductor.

Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators
Abdul-Latif, M. M.; Sanchez-Sinencio, E.

Cyclic-coupled ring oscillators (CCRO) provide several unique features over regular ring oscillators such as availability of multiple sets of phase-shifted outputs and reduced phase noise.  This paper presents CCROs fabricated in a 90 nm digital CMOS process.  The oscillators achieve superior phase noise performance as well as competitive figure-of-merit compared with the state-of-the-art ring oscillators.

A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching
Li, G.; Liu, L.; Tang, Y.; Afshari, E.

This paper presents a low-phase-noise wide-tuning-range oscillator suitable for scaled CMOS processes. The oscillator switches between the two resonant modes of a high-order LC resonator that consists of two identical LC tanks coupled by capacitor and transformer.

A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process
Buckwalter, J. F.; Zheng, X.; Li, G.; Raj, K.; Krishnamoorthy, A. V.

This paper presents a fully-integrated, silicon photonic transceiver using photonic microring resonator modulators for low power consumption.  The transmitter and receiver is demonstrated to data rates of 25 Gb/s with a BER of $10^{-12}$. The total power consumption of the transceiver is 256 mW and demonstrates a link efficiency of 10.2 pJ/bit excluding laser power. At 25 Gb/s, the driver operates at 7.2 pJ/bit.

A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation
Liu, C.; Yan, Y.-P.; Goh, W.-L.; Xiong, Y.-Z.; Zhang, L.-J.; Madihian, M.

This paper presents an automatic gain control (AGC) amplifier with temperature compensation for high-speed applications. The proposed AGC consists of a folded Gilbert variable gain amplifier (VGA), a dc offset canceller, inductorless post amplifiers, a linear open-loop peak detector (PD), an integrator, a symmetrical exponential voltage generator, and a compensation block for temperature stability.

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC
Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.

A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively.  The technique of compensating for low amplifier gain by adjusting the feedback factor could have broad application to other circuits.

A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design
Liu, J.-M.; Chien, S.-H.; Kuo, T.-H.

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems.  Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 $mm^{2}$.  This is a really cool design, but whether or not it is cost effective to do the 25 $mm^{2}$ audio processor in 0.35u is questionable.  Also note the crossed bond wires in the right channel output section of Figure 18.

A 0.18u Monolithic Li-Ion Battery Charger for Wireless Devices Based on Partial Current Sensing and Adaptive Reference Voltage
Pagano, R.; Baker, M.; Radke, R. E.

A Li-ion battery charger based on a charge-control buck regulator operating at 2.2 MHz is presented in this paper.  The novelty of the proposed charge-control converter consists of regulating the average output current by only sensing a portion of the inductor current and using an adaptive reference voltage. By adopting this approach, the charger average output current is set to a constant value of 900 mA regardless of the battery voltage variation.

Efficient Energy Harvesting With Electromagnetic Energy Transducers Using Active Low-Voltage Rectification and Maximum Power Point Tracking
Maurath, D.; Becker, P. F.; Spreemann, D.; Manoli, Y.

This paper reports on efficient interfacing of typical vibration-driven electromagnetic transducers for micro energy harvesting. An adaptive charge pump for dynamic maximum power point tracking is compared with a novel active full-wave rectifier design.  The active diode rectifier achieves efficiencies over 90% at a wide range of input voltage amplitudes of 0.48 V up to 3.3 V. The adaptive charge pump can harvest with a total efficiency of close to 50%, but very independent of the actual buffer voltage.  Results of harvesting from an actual electromagnetic generator prototype are presented.

Electronic Temperature Compensation of Lateral Bulk Acoustic Resonator Reference Oscillators Using Enhanced Series Tuning Technique
Lavasani, H. M.; Pan, W.; Harrington, B. P.; Abdolvand, R.; Ayazi, F.

This paper reports on the demonstration of series tuning for lateral micromechanical oscillators and its application for electronic temperature compensation of piezoelectric lateral bulk acoustic resonator (LBAR) micromechanical oscillators.

# Circuits and Systems II: Volume 59, Issue 5

A K-band CMOS Differential Vackar VCO With the Gate Inductive Feedback
Nguyen, T. N.; Lee, J.-W.

This paper presents a K-band differential Vackar VCO.  You might be thinking, what is a Vackar VCO?  It is just a Colpitts oscillator with a couple of additional capacitors.  This paper adds an additional gate inductor to improve startup performance of the Vackar oscillator.  The phase noise is reported to be several dB better than an equivalent Colpitts.

Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks
Zou, Q.; Ma, K.; Yeo, K. S.; Lim, W. M.

A Ku-band VCO with dual LC tanks is presented in the paper.  A triple-coil transformer provides strong coupling between the two LC tanks.  The claim is made that this architecture provides superior results, but a comparison of other VCOs shows a cross-coupled architecture with similar results.  The phase noise of -117.4dBc/Hz @ 1MHz offset seems to be a conveniently chosen point.  The measured phase noise plot shows several dB worse noise at a frequency offset slightly lower than 1MHz.

A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique
Lee, I-T.; Lu, H.-Y.; Liu, S.-I.

A 6-GHz all-digital fractional-N PLL is presented with a FIR-embedded noise filtering technique.  The measured out-of-band phase noise is improved with the noise filtering circuit.  The benefit of this architecture is unclear, however, because it seems that similar results could be obtained by simply adjusting the PLL bandwidth.

A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers
Ucar, A.; Cetin, E.; Kale, I.

A new continuous-time delta-sigma modulator is presented that is intended for use in RF subsampling receivers. The architecture is analyzed but not realized.  Real time tuning of the loop filter is noted as an obstacle in a practical realization.

Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC
Lee, S. M.; Taleie, S. M.; Saripalli, G. R.; Seo, D.

This paper presents an analysis of DAC output noise that is caused by the phase noise of the DAC clock.  The analysis is presented in the context of phase noise induced by TX leakage, but could apply to other cases as well.

# Circuits and Systems I: Volume 59, Issue 6

A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors
Italia, A.; Ippolito, C. M.; Palmisano, G.

This paper shows a lower power LC VCO with a wide tuning range.  The wide range is achieved by using a switched inductor.  The concept was proven on a 90nm design with a VCO range of 1.13GHz – 1.90GHz.  The results look promising, but may have limited use in higher speed situations where the VCO inductor is small.  In such cases, the switch resistance may cause too much degradation of the tank quality factor for this to be a useful technique.

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector
Tan, Y. S.; Yeo, K. S.; Boon, C. C.; Do, M. A.

This papers shows a dual-loop CDR circuit with a new linear phase detector.  An unbalanced charge pump is used to compensate for the unbalanced pulse-width of the phase detector.

Analysis and Optimization of SFDR in Differential Active-RC Filters

This paper presents a method for optimizing active-RC filters to achieve optimal SFDR.

Design and Analysis of a Class-D Stage With Harmonic Suppression
Fritzin, J.; Svensson, C.; Alvandpour, A.

This papers presents a low-power Class-D stage with low harmonic content in the output waveform.

This papers shows an interesting experimental technique to measure the phase-sensitivity of oscillators to noise signals.  Not sure if this solves a real problem, given the simulation tools that are available that can simulate phase noise with good accuracy.  But from a strictly academic point of view, this is an interest method to verify the fundamentals of phase noise theory that has been presented in other work.

Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems
Weddell, A. S.; Merrett, G. V.; Al-Hashimi, B. M.

The paper describes a photovoltaic (PV) energy harvesting suitable for indoor use.  A maximum power point tracking circuit (MPPT) is shown based on a sample-and-hold circuit.  The sampling frequency and bias current of the MPPT circuit is optimized to allow use in low light (indoor) environments.

A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL
Liu, D.; Basedau, P.; Helfenstein, M.; Wei, J.; Burger, T.; Chen, Y.

This papers presents a model to examine limit cycle and spurious behavior in bang-bang all-digital phase locked loops.  The model utilizes sigma delta modulator (SDM) analysis to capture the quantization effects of the DCO and the bang-bang phase detector.

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver
Chiou, H.-K.; Lin, K.-C.; Chen, W.-H.; Juang, Y.-Z.

This paper describes a biasing technique for a inverter stage that drives a double balanced mixer.  The pmos transistor is biased through a resistor to the output of the inverter.  The nmos transistor is biased separately.

Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints
Bassi, M.; Bevilacqua, A.; Gerosa, A.; Neviani, A.

Great work on a very important public health issue.  Who would have thought that one transceiver architecture would be better than another for Breast Cancer Imaging?

This paper presents an analysis of phase accumulator quantization in a digital to time (DTC) direct frequency synthesizer.  Using the analysis, spur values can be predicted which closely match measured results.  The analysis can also be used for a flying adder synthesizer.

A Gated FM-UWB System With Data-Driven Front-End Power Control
Zhou, B.; Qiao, J.; He, R.; Liu, J.; Zhang, W.; Lv, H.; Rhee, W.; Li, Y.; Wang, Z.

This paper presents a frequency modulated ultra-wideband (FM-UWB) transceiver system with RF submodules gated by a data-driven control signal.  The design utilizes an 8-modulo fractional-N PLL.

# Introduction

This blog is a digest of various analog circuit journals, papers, books, and magazines.  The
initial focus will be on the following IEEE journals:

In the future, we will also cover interesting articles in less academic magazines such as EDN or Nuts and Volts.

We will also accept original papers for publication on this blog.  If you’ve got something that you’d like to submit, let us know!